As the level of integration of semiconductors becomes higher, the number of input/output terminals increases. A need has therefore arisen for a semiconductor package having many input/output terminals. In general, input/output terminals can be divided into two types, one being those arranged in a single row along a periphery of a package and the other being those arranged in multiple arrays not only along a periphery of a package but also inside the package. The former is typified by QFPs (Quad Flat Packages). To provide them with many terminals, it is necessary to reduce the pitch of the the terminals. In a pitch range of 0.5 mm and shorter, an advanced technique is required for their connection with a printed board. The latter array type permits arranging terminals at a relatively large pitch and is hence suited for a high pin count.
Among such array types, PGAs (Pin Grid Array) which are provided with connecting pins have heretofore been commonly used. However, their connections with printed boards are conducted by insertion, so that they are not suited for surface mounting. To overcome this inconvenience, packages called BGAs (Ball Grid Arrays) which permit surface mounting have been developed. These BGAs can be classified into (1) the ceramic type, (2) the printed wiring board type and (3) the tape type making use of TAB (tape automated bonding). Of these, the ceramic type has a shorter distance between a mother board and a package compared with the conventional PGAs so that a warp in the package due to a difference in thermal stress between the mother board and the package remains a serious problem. Further, the printed wiring board type is also accompanied by problems such as substrate warping, low moisture resistance, low reliability and large substrate thickness. Tape BGAs making use of the TAB technology have therefore been proposed.
With a view to meeting a further reduction in the package size, packages having substantially the same size as semiconductor chips, namely, so-called chip size packages (CSP) have been proposed. Each of them has connecting portions, which are to be connected with an external printed board, in a mounting area rather than at a peripheral portion of a semiconductor chip.
Specific examples of such CSPs include those fabricated by bonding a bumped polyimide film to a surface of a semiconductor chip, establishing electrical connection with the chip and gold lead wires, and potting an epoxy resin or the like to seal the resultant package (NIKKEI MATERIALS & TECHNOLOGY, No. 140, pp. 18–19, April, 1994) and those obtained by forming metal bumps on a temporary substrate at positions corresponding to points of connection between a semiconductor chip and an external printed board, bonding the semiconductor chip facedown, and subjecting it to transfer molding on the temporary substrate (Smallest Flip-Chip-Like Package CSP; The Second VLSI Packaging Workshop of Japan, pp. 46–50, 1994).
On the other hand, packages making use of a polyimide tape as a base film are studied in the fields of BGAs and CSPs as mentioned above. In this case, as the polyimide tape, one having a copper foil laminated on a polyimide film via an adhesive layer is commonly employed. However, from the viewpoint of heat resistance and moisture resistance, one having a polyimide layer formed directly on a copper foil, that is, a so-called two-layer flexible base material, is preferred. Production processes of such two-layer flexible base materials are roughly divided into (1) a process in which polyamic acid as a precursor for a polyimide is coated on a copper foil and is then hardened and (2) a process in which a thin metal film is formed on a hardened polyimide film by vacuum deposition or electroless plating. To provide, for example, holes reaching the copper foil by removing the polyimide at desired portions (which correspond to portions capable of exhibiting a second connecting function) while applying laser beam machining, it is preferred to make the polyimide film as thin as possible. In contrast, upon forming a two-layer flexible base material into the form of a leadframe and handling the same, a base film of a small thickness involves problems such as low handling readiness and insufficient rigidity as a frame.
As has been described above, various proposals have been made as semiconductor packages capable of meeting miniaturization and high integration. Nevertheless, further improvements are desired to provide satisfaction in all aspects such as performance, characteristics and productivity.
An object of the present invention is to provide a process for the fabrication of a semiconductor package, the process making it possible to stably fabricate with good productivity semiconductor packages capable of meeting miniaturization and high integration, and also to provide such a semiconductor package.